New Compact Model for Generation Drain Current Transients in Weak and Moderate Inversions of Submicron Floating-Body PD SOI MOSFETs

In this paper, generation-type drain current transients, in advanced (down to 50nm gate-length) floating-body PD SOI MOSFETs are investigated by 2D numerical simulation in weak inversion operation. An original compact analytical model is derived for the pure transient weak inversion operation and validated on both elementary and realistic 2D structures. The proposed sub-threshold transient compact model allows accurately to predict the influence of the generation lifetime, surface velocity (or interface state density), oxide thickness and substrate doping on floating-body related transient behavior and duration, which is essential for advanced transistor optimization and subsequent circuit applications. Moreover, our model is a unique, robust tool for the electrical characterization of submicron SOI transistors since it allows the carrier lifetime extraction independently on the channel carrier mobility and device effective gate length.